High level architecture

image00

The internal CPU architecture is 4 bits, but the address space is 8 bits.

I included two buses. There is a data bus for moving data inside the CPU and a system bus for communicating with main memory and other components. The system bus can only read and write from Register A. The address to read/write to is dictated by a combination of the segment register (SR) and bus address register (BA). I/O devices will be memory mapped.

Instructions are stored in a dedicated memory with 8 bit address space. The instruction pointer (IP, 8 bits) controls the next address to load. Instructions are 8 bits each. The upper bits are loaded into the instruction register and the lower bits are loaded into the argument register. Only the control logic can access the instruction, but if the argument is a literal, it may be written to the data bus. Alternatively the argument can be used by the control logic to direct ALU or system bus activity.

Because the instruction address space is 8 bits, but an instruction can only have a 4 bit argument, I’m including a jump segment register (JSR) to hold the high bits of the jump address.

Register A is used as the accumulator for the ALU. There will be an input latch inside the ALU so two arguments can be successively loaded from the data bus. The first argument will be latched and the second will be input directly from the bus. Lastly, there is a 4 bit flags register which is controlled by the ALU and readable by the control logic.