I’ve decided to fulfill my childhood dream of building a CPU from scratch. I’m fascinated by the fundamentals of how computers, math, and nature work so this project is a natural fit for me. Originally I was going to use 7400 logic chips, but after finding several blogs of people who have used discrete components, I’ve decided to go that route. I know that will increase the complexity, cost, and reduce the operating speed, but it will also give me a chance to dig deeper into the subject.
The ALU will be 4 bits, but I’ll use a segment register to achieve an 8 bit address bus. If I find this too restricting, I may move to a 12 bit bus, but for starting out I’ll limit myself to 8 bits even though that doesn’t give me much address space.
The instruction memory will be separate from data memory. I’ll initially use a memory chip so I can focus on the CPU architecture. Eventually I would like to try building out a small amount of SRAM and DRAM to learn about it.
I/O operations will be memory mapped. I’ll reserve some of the address segments I/O devices.
Instructions will be 8 bits. The upper 4 bits will be instruction only and the lower 4 bits will either be a literal or a command for the ALU. The supported ALU operations will take 3 instructions to encode: addition, comparison, and the four boolean operations: not, and, or, xor. There will be four data registers (A, B, C, D) with A being used as the accumulator.
I/O operations will always read and write to the accumulator register.
There are five additional control registers:
- Instruction Pointer (8 bits)
- Jump Segment Register (4 bits) – upper 4 bits of jump address
- Segment Register (4 bits) – upper 4 bits of address bus
- Memory Address (4 bits) – lower 4 bits of address bus
- Flags (4 bits) – Set by the ALU: overflow, greater than, less than, zero
For I/O I intend to support a serial port, GPIO ports, and two ADCs.
Inspired by the Apollo Guidance Computer, I’m going to use RTL logic. My base building block will be NOR/NOT gates. Because RTL is power hungry, my goal is to keep power consumption low at the cost of speed. At this point I don’t know what a realistic clock rate will be (50 KIPS?) or what kinds of programs I’ll be able to run, but I envision the computer to basically be more of an instrument controller than a general purpose CPU. I won’t be implementing interrupts or a stack so I’m very limited in program architecture.
In addition to instrument control, two stretch projects would be outputting vector graphics to an X-Y scope (via the ADCs) and keeping a quadcopter level. (How can I be inspired by the Apollo guidance computer and not try to land something?)