Latching ALU arguments

My ALU design requires to clock cycles to load the arguments. In the first clock cycle, the first argument is placed on the data bus and latched by the argument latch. In the second clock cycle, the second argument is placed on the bus and the ALU is enabled.

Here is a simulation of the circuit:


Set A, 5
Set B, 7
Add A, B (2 clock cycles)
  -> moves A to latch
  -> adds B and latch; stores result in A
Result: 5 + 7 = 0xC